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 NTD14N03R Power MOSFET 14 Amps, 25 Volts
N-Channel DPAK
Features
* * * * *
Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High-Efficiency DC-DC Converters
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14 AMPERES, 25 VOLTS RDS(on) = 70.4 mW (Typ)
N-CHANNEL D
MAXIMUM RATINGS (TJ = 25C unless otherwise specified)
Parameter Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance - Junction-to-Case Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C, Chip - Continuous @ TA = 25C, Limited by Package - Single Pulse (tp 10 ms) Thermal Resistance - Junction-to-Ambient (Note 1) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Thermal Resistance - Junction-to-Ambient (Note 2) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RqJC PD ID ID ID RqJA PD ID RqJA PD ID TJ, Tstg TL Value 25 20 6.0 20.8 14 11.4 28 80 1.56 3.1 120 1.04 2.5 -55 to 150 260 Unit Vdc Vdc C/W W A A A C/W W A C/W W A C C 12 3 CASE 369C DPAK (Surface Mount) STYLE 2 S 4 4 G
1 2 3 CASE 369D DPAK (Straight Lead) STYLE 2
MARKING DIAGRAM & PIN ASSIGNMENTS
4 Drain YWW T14 N03 4 Drain YWW T14 N03 3 Source 1 Gate 2 Drain 3 Source Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel Publication Order Number: NTD14N03R/D
1. When surface mounted to an FR4 board using 0.5 sq. in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. 1 Gate
2 Drain
14N03 Y WW
= Device Code = Year = Work Week
ORDERING INFORMATION
Device NTD14N03R NTD14N03R-1 NTD14N03RT4
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 3
NTD14N03R
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Characteristics OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 4.5 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 5 Adc) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VGS = 5 Vdc, ID = 5 Adc, VDS = 10 Vdc) (Note 3) SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 5 Adc, VGS = 0 Vdc) (Note 3) (IS = 5 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - trr (IS = 5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. ta tb QRR - - - - 0.93 0 93 0.82 6.6 4.75 1.88 0.002 1.2 12 - - - - - mC Vdc (VGS = 10 Vdc, VDD = 10 Vdc, ID = 5 Adc, RG = 3 W) td(on) tr td(off) tf QT Q1 Q2 - - - - - - - 3.8 27 9.6 2.0 1.8 0.8 0.7 - - - - - - - nC ns ( (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) , , ) Ciss Coss Crss - - - 115 62 33 - - - pF VGS(th) 1.0 - RDS(on) - - gFS - 7.0 - 117 70.4 130 95 Mhos 1.5 - 2.0 - Vdc mV/C mW V(br)DSS 25 - IDSS - - IGSS - - - - 1.0 10 100 nAdc 28 - - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time
ns
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2
NTD14N03R
14 ID, DRAIN CURRENT (AMPS) 12 10 8 6 4 3V 2 VGS = 2.5 V 0 0 2 4 6 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 0 1 2 3 4 5 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 V 8V 7V 6V 14 5V ID, DRAIN CURRENT (AMPS) 12 10 8 6 TJ = 25C 4 2 TJ = 125C TJ = -55C VDS 10 V
4.5 V 4V 3.5 V
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.20 VGS = 10 V 0.16
0.20 TJ = 125C 0.16 TJ = 25C
0.12
TJ = 125C TJ = 25C TJ = -55C
0.12
0.08
0.08
TJ = -55C
0.04 0 0 2 4 6 8 10 12 14 ID, DRAIN CURRENT (AMPS)
0.04 VGS = 4.5 V 0 0 2 4 6 8 10 12 14 ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1 0.8 0.6 -50 10 -25 0 25 50 75 100 125 150 0 ID = 5 A VGS = 10 V IDSS, LEAKAGE (nA) 1000
Figure 4. On-Resistance versus Drain Current and Temperature
VGS = 0 V
TJ = 150C
100
TJ = 125C
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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3
NTD14N03R
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
200 VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) 160 Ciss Crss 120
TJ = 25C
8
6 QT 4 Q1 Q2 VGS
Ciss
80
Coss Crss
40 0 10 5 VGS 0 VDS 5 10 15
2 ID = 5 A TJ = 25C 0 0 0.4 0.8 1.2 1.6 2.0 Qg, TOTAL GATE CHARGE (nC)
20
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
100 IS, SOURCE CURRENT (AMPS) VDS = 10 V ID = 5 A VGS = 10 V tr t, TIME (ns)
70 VGS = 0 V 60 50 40 30 TJ = 150C 20 10 0 1 10 RG, GATE RESISTANCE (W) 100 0 0.2 0.4 0.6 TJ = 25C 0.8 1.0
10
td(off) td(on) tf
1
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
6.20 0.244
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
3.0 0.118
2.58 0.101
5.80 0.228
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
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4
NTD14N03R
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE) CASE 369C ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
-T- B V R
4
SEATING PLANE
C E
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K L R S U V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
DPAK (SINGLE GAUGE) CASE 369D ISSUE O
SCALE 1:1 B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
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5
NTD14N03R
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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6
NTD14N03R/D


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